Be responsible for digital design of image sensor, SoC integration and IP design, analysis, integration, and validation. Work closely with back-end team in floor-planning, timing closure and DFT.
Conduct image sensor array/analog related timing control design and STA.
Perform chip bring-up, validation and debugging. Design, integrate and validate ISP data pipes according to PRD/design specification and system architecture of SoC CIS products, following ASIC design flow: coding, simulation, synthesis, static timing analysis, formality verification, DFT, using Simvision, EDA tools such as Prime Time, cadence Virtuoso, Design Compiler, Integrator, and Verilog and System Verilog programming languages etc.
Conduct design verification and modeling using SVA, Python, Perl.
Work with sensor digital and analog engineers for system design, integration and validation. Work with algorithm engineers for module level design, including hardware C model implementation, micro architecture design, RTL design and hardware/software co-simulation. Work with algorithm andapplication engineers for image tuning and qualification. Conduct silicon validation, debugging and tuning.
Bachelor's degree in Electrical Engineering, Computer Engineering, or related fields with course work of Digital Imaging Processing, Logic Design, VLSI, Analog and Digital Circuits, and two (2) years of digital design experience.
Will accept a Master's degree in the same disciplines in lieu of the 2 years of experience.
Required experience or skills:
Modern design methodology – RTL, ASMs, Verilog;
Semiconductor device physics and MOS modeling, Static and dynamic CMOS combinational logic gate, capacitance, and switch level modeling, latches and clocking, Cadence Composer for schematic entry, Cadence virtuoso for layout design, Cadence Spectre for circuit simulation, Mentor Calibre for layout verification, Mentor xRC for extraction;
Verilog coding, circuit netlist scripting, SPICE simulation, logic synthesis, static and dynamic timing/power analysis, library characterization, placement and routing(P&R), parasitic extraction, parasitic-annotated simulation;
Python scripting; Matlab simulation.
Annual base salary for this role in California, US is expected to be between $126,984 - $130,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.
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